The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present CELOC, a Clock-Enabled Low-Overhead Communication technique. It is a network access technique that uses the clock buffers of an FPGA as serial communication links in order to reduce the overhead contributed by the NoC links. This technique involves toggling the clock enables of clock buffers to transmit communication signals from one circuit to another. A demonstrator based on a Xilinx 7 series FPGA showed that a single link can achieve a bandwidth of 6.5 Gbps at 100 MHz.