Clock Buffers, Nets, and Trees for On-Chip Communication: A Novel Network Access Technique in FPGAs

Adewale Adetomi*, Godwin Enemali, Tughrul Arslan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The number of IPs running concurrently on an FPGA has increased in recent years. Communication among these IPs has necessitated the introduction of the network on chip (NoC) for low-power, high-performance, and scalable on-chip networking. While NoCs are superior to traditional shared buses, there is an attendant resource overhead incurred by the NoC links, routers and network adapters. We present CELOC, a Clock-Enabled Low-Overhead Communication technique. It is a network access technique that uses the clock buffers of an FPGA as serial communication links in order to reduce the overhead contributed by the NoC links. This technique involves toggling the clock enables of clock buffers to transmit communication signals from one circuit to another. A demonstrator based on a Xilinx 7 series FPGA showed that a single link can achieve a bandwidth of 6.5 Gbps at 100 MHz.

Original languageEnglish
Title of host publication2017 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS (IPDPSW)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages219-222
Number of pages4
DOIs
Publication statusPublished - 2017
Event31st IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS) - Orlando
Duration: 29 May 20172 Jun 2017

Publication series

NameIEEE International Symposium on Parallel and Distributed Processing Workshops
PublisherIEEE
ISSN (Print)2164-7062

Conference

Conference31st IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPS)
CityOrlando
Period29/05/172/06/17

Keywords

  • CELOC
  • clock buffers
  • on-chip communication
  • network on chip
  • NoC link
  • low overhead

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