Compiler Parallelization of C Programs for Multi-core DSPs with Multiple Address Spaces

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper develops a new approach to compiling C programs for multiple address space, multi-processor DSPs. It integrates a novel data transformation technique that exposes the processor location of partitioned data into a parallelization strategy. When this is combined with a new address resolution mechanism, it generates efficient programs that run on multiple address spaces without using message passing. This approach is applied to the UTDSP benchmark suite and evaluated on a four processor TigerSHARC board, where it is shown to outperform existing approaches and gives an average speedup of 3.25 on the parallel benchmarks.
Original languageEnglish
Title of host publicationCODES+ISSS '03 Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
PublisherACM
Pages219-224
Number of pages6
ISBN (Print)1-58113-742-7
DOIs
Publication statusPublished - Mar 2003

Keywords

  • DSPs, address resolution, data partitioning, multiple address space compilation

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