Compiler Reduction of Invalidation Traffic in Virtual Shared Memory Systems

Michael F. P. O'Boyle, Rupert W. Ford, Andy Nisbet

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents new compiler analysis for the elimination of invalidation traffic in virtual shared memory, using a hybrid distributed invalidation coherence scheme. The invalidation and acknowledgement messages are removed; this reduces both network invalidation traffic and the latency of a write fault. It aggressively exploits the SPMD execution model and uses array section analysis to accurately determine only those instances when invalidation is necessary, thus avoiding the additional read misses of previous schemes. Equations determining precisely what data should be invalidated are presented and translated into a form amenable to compiler analysis. Preliminary experimental results on a 30 node prototype architecture demonstrate the performance attainable using this scheme.
Original languageEnglish
Title of host publicationEuro-Par'96 Parallel Processing
Subtitle of host publicationSecond International Euro-Par Conference Lyon, France, August 26–29 1996 Proceedings, Volume I
PublisherSpringer Berlin Heidelberg
Number of pages9
ISBN (Electronic)978-3-540-70633-5
ISBN (Print)978-3-540-61626-9
Publication statusPublished - 1996

Publication series

NameLecture Notes in Computer Science
PublisherSpringer Berlin Heidelberg
ISSN (Print)0302-9743

Fingerprint Dive into the research topics of 'Compiler Reduction of Invalidation Traffic in Virtual Shared Memory Systems'. Together they form a unique fingerprint.

Cite this