Abstract
Sparse matrix-vector multiplication (SpMV) is a critical building block for iterative graph analytics algorithms. Typically, such algorithms have a varying active vertex set across iterations. This variablity has been used to improve performance by either dynamically switching algorithms between iterations (software) or designing custom accelerators (hardware) for graph analytics algorithms. In this work, we propose a novel framework, CoSPARSE, that employs hardware and softwarere configuration as a synergistic solution to accelerate SpMV-based graph analytics algorithms. Building on previously proposed general-purpose reconfigurable hardware, we implement CoSPARSE as a software layer, abstracting the hardware as a specialized SpMV accelerator. CoSPARSE dynamically selects software and hardware configurations for each iteration and achieves a maximum speedup of 2.0× compared to the naïve implementation with no reconfiguration. Across a suite of graph algorithms, CoSPARSE outperforms a state-of-the-art shared memory framework, Ligra, on a Xeon CPU with up to 3.51× better performance and 877× better energy efficiency.
Original language | English |
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Title of host publication | 2021 58th ACM/IEEE Design Automation Conference (DAC) |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 949-955 |
Number of pages | 6 |
ISBN (Electronic) | 978-1-6654-3274-0 |
ISBN (Print) | 978-1-6654-3275-7 |
DOIs | |
Publication status | Published - 13 Nov 2021 |
Event | 58th Design Automation Conference - San Francisco, United States Duration: 5 Dec 2021 → 9 Dec 2021 https://www.dac.com/ |
Publication series
Name | |
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ISSN (Print) | 0738-100X |
Conference
Conference | 58th Design Automation Conference |
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Abbreviated title | DAC 2021 |
Country/Territory | United States |
City | San Francisco |
Period | 5/12/21 → 9/12/21 |
Internet address |