DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches

Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Spin-Transfer Torque RAM (STT-RAM) exhibits advantages like high density, non-volatility, and low leakage power consumption, making them a plausible successor to SRAM in caches. However, STT-RAM's large write energy and latency constrain its potential for commercial usage in caches. Relaxing STTRAM's retention time is one of the emerging and viable solutions to alleviate this roadblock, as this reduces the write time and energy. Reduction of retention time, however, leads to premature expiry of blocks requiring frequent refreshes or writebacks. These approaches cause unnecessary stalls and increase miss-rate.This paper proposes using a cache with partitions of different retention times. It further puts forth a block placement and reallocation policy to use these different partitions effectively. A block is said to be placed in an optimal partition if the block is either accessed or evicted before it expires. In particular, infrequently written blocks are allocated to higher retention time partitions, guaranteeing a reduction in block expiry/writebacks. During the execution, at regular intervals, blocks are migrated to appropriate retention time partitions depending on the application characteristics. Experimental evaluation shows significant improvement in performance and miss-rate compared to baseline allocation policies.
Original languageEnglish
Title of host publication2021 22nd International Symposium on Quality Electronic Design (ISQED)
PublisherIEEE
Pages469-475
Number of pages7
ISBN (Electronic)978-1-7281-7641-3, 978-1-7281-7640-6
ISBN (Print)978-1-7281-7642-0
DOIs
Publication statusPublished - 10 May 2021
Event22nd International Symposium on Quality Electronic Design - Santa Clara, United States
Duration: 7 Apr 20219 Apr 2021
Conference number: 22

Publication series

NameIEEE International Symposium on Quality Electronic Design
PublisherIEEE
ISSN (Print)1948-3287

Conference

Conference22nd International Symposium on Quality Electronic Design
Abbreviated titleISQED 2021
Country/TerritoryUnited States
CitySanta Clara
Period7/04/219/04/21

Keywords / Materials (for Non-textual outputs)

  • STT-RAM
  • last level cache
  • multi-retention
  • low leakage
  • write latency
  • write frequency
  • dynamic allocation

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