DCA: a DRAM-Cache-Aware DRAM Controller

Cheng-Chieh Huang, Vijayanand Nagarajan, Arpit Joshi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

3D-stacking technology has enabled the option of embedding a large DRAM cache onto the processor. Since the DRAM cache can be orders of magnitude larger than a conventional SRAM cache, the size of its cache tags can also be large. Recent works have proposed storing these tags in the stacked DRAM array itself. However, this increases the complexity of a DRAM cache request, which now translates into multiple DRAM cache accesses (tag/data).
In this work, we address how to schedule these DRAM cache accesses. We start by exploring whether or not a conventional DRAM controller will work well. We introduce two potential baseline designs and study their limitations. We then derive a set of design principles that a DRAM cache controller must ideally satisfy. Our DRAM-cache-aware (DCA) DRAM controller, that is based on these principles, consistently improves performance over various DRAM cache organizations.
Original languageEnglish
Title of host publicationSC '16 Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis
Place of PublicationSalt Lake City, UT, USA
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages887-897
Number of pages11
ISBN (Electronic)978-1-4673-8815-3
ISBN (Print)978-1-4673-8816-0
DOIs
Publication statusPublished - 16 Mar 2017
EventProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis 2016 - Salt Lake City, United States
Duration: 13 Nov 201618 Nov 2016
http://sc16.supercomputing.org/

Publication series

Name
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISSN (Electronic)2167-4337

Conference

ConferenceProceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis 2016
Abbreviated titleSC 2016
CountryUnited States
CitySalt Lake City
Period13/11/1618/11/16
Internet address

Keywords

  • DRAM Cache
  • Die-stacked DRAM
  • Memory System

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