Delta-Sigma Modulator Design Using a Memristive FIR DAC

Danyu Wang, Shiwei Wang, Themis Prodromakis, Christos Papavasilliou

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

This paper proposes the design of a first-order single-bit continuous-time Delta-Sigma modulator using a memristive finite impulse response (FIR) digital-to-analog converter (DAC) in the feedback. To achieve better power and circuit area efficiency, the coefficients of the 8-tap FIR filter are implemented using memristors with programmable resistance in the range of 17.20kΩ to 55.63kΩ . The modulator was designed and simulated using a 180nm standard CMOS technology in addition to a memristor model, which was constructed based on the measured characteristics of the real device behavior. The modulator targets 10kHz signal bandwidth and samples at 10MHz. Simulation results show that the FIR DAC can improve the modulator signal-to-noise and distortion ratio (SNDR) from 44.36dB to 62.29dB with the existence of 5ns RMS jitter at the sampling clock. The FIR DAC still contributes to a better modulator SNDR performance even considering a worst-case 20% resistance variation of the memristors.
Original languageEnglish
Title of host publication2022 29th IEEE International Conference on Electronics, Circuits and Systems (ICECS)
Publication statusE-pub ahead of print - 12 Dec 2022


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