Design and analysis of a frequency division and duty cycle control circuit for on-chip signal synthesis

Rui Song, Jun Zhang, Jie Tong, Minghao Zhang, Sandy Cochran, Ian Underwood

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

In this article, a complementary metal–oxide–semiconductor (CMOS) frequency and duty cycle controller (FDCC) is presented for on-chip signal synthesis. The circuit consists of a few logic gates and a voltage-controlled oscillator, and is functionally similar to a programmable divide-by-N frequency divider. It is designed for driving integrated sensor and actuator systems. Compared with other frequency dividers with the same control flexibility, the proposed circuit features a compact topology and allows the control over the output signal duty cycle. For the proof-of-concept, a prototype 1 × 4 array of identical FDCCs has been fabricated on a Austria Mikro Systeme (AMS) CMOS process. Each FDCC occupies an active area of , which is area-efficient. The array has been validated to generate 4 synchronized outputs with a duty cycle tuning range of . Although driven by a 5- power supply, it still provides a relatively high power-efficiency of .
Original languageEnglish
Pages (from-to)115-125
JournalIntegration
Volume90
Early online date27 Jan 2023
DOIs
Publication statusPublished - May 2023

Keywords / Materials (for Non-textual outputs)

  • Frequency control
  • Duty cycle control
  • Programmable divide-by-N frequency divider
  • Clock generation
  • Signal synthesis

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