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Abstract / Description of output
In this article, a complementary metal–oxide–semiconductor (CMOS) frequency and duty cycle controller (FDCC) is presented for on-chip signal synthesis. The circuit consists of a few logic gates and a voltage-controlled oscillator, and is functionally similar to a programmable divide-by-N frequency divider. It is designed for driving integrated sensor and actuator systems. Compared with other frequency dividers with the same control flexibility, the proposed circuit features a compact topology and allows the control over the output signal duty cycle. For the proof-of-concept, a prototype 1 × 4 array of identical FDCCs has been fabricated on a Austria Mikro Systeme (AMS) CMOS process. Each FDCC occupies an active area of , which is area-efficient. The array has been validated to generate 4 synchronized outputs with a duty cycle tuning range of . Although driven by a 5- power supply, it still provides a relatively high power-efficiency of .
Keywords / Materials (for Non-textual outputs)
- Frequency control
- Duty cycle control
- Programmable divide-by-N frequency divider
- Clock generation
- Signal synthesis
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- 1 Finished
Murray, A., Smith, S. & Walton, A.
27/05/13 → 31/05/19