Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps

Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis

doi:10.1109/TCSI.2021.3122343

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps

Sachin Maheshwari^*, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

^*Corresponding author for this work

School of Engineering

Research output: Contribution to journal › Article › peer-review

Abstract / Description of output

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

Original language	English
Pages (from-to)	4862-4875
Number of pages	14
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	68
Issue number	12
Early online date	2 Nov 2021
DOIs	https://doi.org/10.1109/TCSI.2021.3122343
Publication status	Published - 1 Dec 2021

Keywords / Materials (for Non-textual outputs)

EDA tools
hybrid CMOS/memristor
modelling
verification

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10.1109/TCSI.2021.3122343

Cite this

Maheshwari, S., Stathopoulos, S., Wang, J., Serb, A., Pan, Y., Mifsud, A., Leene, L. B., Shen, J., Papavassiliou, C., Constandinou, T. G., & Prodromakis, T. (2021). Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(12), 4862-4875. https://doi.org/10.1109/TCSI.2021.3122343

@article{cf45e5d4ac1a4e858c20c840035bca67,

title = "Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps",

abstract = "Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.",

keywords = "EDA tools, hybrid CMOS/memristor, modelling, verification",

author = "Sachin Maheshwari and Spyros Stathopoulos and Jiaqi Wang and Alexander Serb and Yihan Pan and Andrea Mifsud and Leene, {Lieuwe B.} and Jiawei Shen and Christos Papavassiliou and Constandinou, {Timothy G.} and Themistoklis Prodromakis",

note = "Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

year = "2021",

month = dec,

day = "1",

doi = "10.1109/TCSI.2021.3122343",

language = "English",

volume = "68",

pages = "4862--4875",

journal = "IEEE Transactions on Circuits and Systems I: Regular Papers",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers",

number = "12",

}

Maheshwari, S, Stathopoulos, S, Wang, J, Serb, A, Pan, Y, Mifsud, A, Leene, LB, Shen, J, Papavassiliou, C, Constandinou, TG & Prodromakis, T 2021, 'Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 4862-4875. https://doi.org/10.1109/TCSI.2021.3122343

TY - JOUR

T1 - Design Flow for Hybrid CMOS/Memristor Systems - Part I

T2 - Modeling and Verification Steps

AU - Maheshwari, Sachin

AU - Stathopoulos, Spyros

AU - Wang, Jiaqi

AU - Serb, Alexander

AU - Pan, Yihan

AU - Mifsud, Andrea

AU - Leene, Lieuwe B.

AU - Shen, Jiawei

AU - Papavassiliou, Christos

AU - Constandinou, Timothy G.

AU - Prodromakis, Themistoklis

PY - 2021/12/1

Y1 - 2021/12/1

N2 - Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

AB - Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

KW - EDA tools

KW - hybrid CMOS/memristor

KW - modelling

KW - verification

UR - http://www.scopus.com/inward/record.url?scp=85118658948&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2021.3122343

DO - 10.1109/TCSI.2021.3122343

M3 - Article

AN - SCOPUS:85118658948

SN - 1549-8328

VL - 68

SP - 4862

EP - 4875

JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

IS - 12

ER -

Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps

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