Design Flow for Hybrid CMOS/Memristor Systems - Part I: Modeling and Verification Steps

Sachin Maheshwari*, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.

Original languageEnglish
Pages (from-to)4862-4875
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Issue number12
Early online date2 Nov 2021
Publication statusPublished - 1 Dec 2021

Keywords / Materials (for Non-textual outputs)

  • EDA tools
  • hybrid CMOS/memristor
  • modelling
  • verification


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