Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout

Sachin Maheshwari; Spyros Stathopoulos; Jiaqi Wang; Alexander Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G. Constandinou; Themistoklis Prodromakis

doi:10.1109/TCSI.2021.3122381

Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout

Sachin Maheshwari^*, Spyros Stathopoulos, Jiaqi Wang, Alexander Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themistoklis Prodromakis

^*Corresponding author for this work

School of Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

Original language	English
Pages (from-to)	4876-4888
Number of pages	13
Journal	IEEE Transactions on Circuits and Systems I: Regular Papers
Volume	68
Issue number	12
Early online date	2 Nov 2021
DOIs	https://doi.org/10.1109/TCSI.2021.3122381
Publication status	Published - 1 Dec 2021

Keywords / Materials (for Non-textual outputs)

CAD tool
circuit design
hybrid CMOS/memristor
in-memory computation
low-power
RRAM

Access to Document

10.1109/TCSI.2021.3122381

Cite this

Maheshwari, S., Stathopoulos, S., Wang, J., Serb, A., Pan, Y., Mifsud, A., Leene, L. B., Shen, J., Papavassiliou, C., Constandinou, T. G., & Prodromakis, T. (2021). Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout. IEEE Transactions on Circuits and Systems I: Regular Papers, 68(12), 4876-4888. https://doi.org/10.1109/TCSI.2021.3122381

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title = "Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout",

abstract = "The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.",

keywords = "CAD tool, circuit design, hybrid CMOS/memristor, in-memory computation, low-power, RRAM",

author = "Sachin Maheshwari and Spyros Stathopoulos and Jiaqi Wang and Alexander Serb and Yihan Pan and Andrea Mifsud and Leene, {Lieuwe B.} and Jiawei Shen and Christos Papavassiliou and Constandinou, {Timothy G.} and Themistoklis Prodromakis",

note = "Funding Information: This work was supported in part by the Engineering and Physical Sciences Research Council (EPSRC) Programme under Functional Oxide Reconfigurable Technologies (FORTE) Grant EP/R024642/1, in part by a SYnaptically connected brain-silicon Neural Closed-loop Hybrid system (SYNCH) under Grant H2020-FETPROACT-2018-01, and in part by the RAEng Chair in Emerging Technologies under Grant CiET1819/2/93. Publisher Copyright: {\textcopyright} 2004-2012 IEEE.",

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Maheshwari, S , Stathopoulos, S, Wang, J, Serb, A, Pan, Y, Mifsud, A, Leene, LB, Shen, J, Papavassiliou, C, Constandinou, TG & Prodromakis, T 2021, 'Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout', IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 12, pp. 4876-4888. https://doi.org/10.1109/TCSI.2021.3122381

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T1 - Design Flow for Hybrid CMOS/Memristor Systems - Part II

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AU - Maheshwari, Sachin

AU - Stathopoulos, Spyros

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AU - Serb, Alexander

AU - Pan, Yihan

AU - Mifsud, Andrea

AU - Leene, Lieuwe B.

AU - Shen, Jiawei

AU - Papavassiliou, Christos

AU - Constandinou, Timothy G.

AU - Prodromakis, Themistoklis

N1 - Funding Information: This work was supported in part by the Engineering and Physical Sciences Research Council (EPSRC) Programme under Functional Oxide Reconfigurable Technologies (FORTE) Grant EP/R024642/1, in part by a SYnaptically connected brain-silicon Neural Closed-loop Hybrid system (SYNCH) under Grant H2020-FETPROACT-2018-01, and in part by the RAEng Chair in Emerging Technologies under Grant CiET1819/2/93. Publisher Copyright: © 2004-2012 IEEE.

PY - 2021/12/1

Y1 - 2021/12/1

N2 - The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

AB - The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.

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JO - IEEE Transactions on Circuits and Systems I: Regular Papers

JF - IEEE Transactions on Circuits and Systems I: Regular Papers

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Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout

Abstract

Keywords / Materials (for Non-textual outputs)

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FORTE: Functional Oxide Reconfigurable Technologies (FORTE): A Programme Grant

Cite this

Design Flow for Hybrid CMOS/Memristor Systems - Part II: Circuit Schematics and Layout

Abstract

Keywords / Materials (for Non-textual outputs)

Access to Document

Other files and links

Fingerprint

Projects

FORTE: Functional Oxide Reconfigurable Technologies (FORTE): A Programme Grant

Cite this