Design-Space Exploration of Resource-Sharing Solutions for Custom Instruction Set Extensions

Marcela Zuluaga, Nigel Topham

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

Customized processor performance generally increases as additional custom instructions are added. However, performance is not the only metric that modern systems must take into account; die area and energy efficiency are equally important. Resource sharing during synthesis of instruction set extensions (ISEs) can significantly reduce the die area and energy consumption of a customized processor. This may increase the number of custom instructions that can be synthesized with a given area budget. Resource sharing involves combining the graph representations of two or more ISEs which contain a similar subgraph. This coupling of multiple subgraphs, if performed naively, can increase the latency of the extension instructions considerably, and yet, as we show in this paper, an appropriate level of resource sharing provides a significantly simpler design with modest increases in average latency for ISEs. Our main contributions are the introduction of a parametric method for exploring the tradeoffs that can be achieved between instruction latency and implementation complexity, and the coupling of design-space exploration with fast area-delay models for the operators comprising each ISE. We present experimental evidence that our heuristic exposes a broad range of design points, allowing advantageous tradeoffs between die area and latency to be found and exploited.
Original languageEnglish
Pages (from-to)1788-1801
Number of pages14
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number12
Publication statusPublished - 1 Dec 2009

Keywords / Materials (for Non-textual outputs)

  • ASIC
  • SoC
  • custom instruction set extension synthesis
  • customized processor performance
  • design-space exploration
  • die area
  • energy consumption
  • energy efficiency
  • fast area-delay model
  • graph representation
  • implementation complexity
  • instruction latency
  • parametric method
  • resource-sharing solution
  • circuit complexity
  • graph theory
  • high level synthesis
  • instruction sets
  • integrated circuit design
  • microprocessor chips
  • resource allocation
  • system-on-chip


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