Abstract / Description of output
In the quest for greater performance, superscalar
processor designers implement large issue queues and
register files to take advantage of the out-of-order execution
of the architecture. However, there is a trade-off to
be made as performance gains are achieved at the cost
of increased energy consumption. There comes a point
where increasing the size of these structures is too costly
in terms of energy. Recently proposed compiler-directed
optimisations can be used to reduce this overhead. Conversely,
for the same energy consumption, larger issue
queues and register files can be used to increase performance.
This paper considers the design space of issue queue
and register file sizes in processors implementing a combination
of issue queue throttling and early register releasing
schemes under compiler control. Compared with
the best baseline containing 64 issue queue entries and
96 integer registers, our scheme with a configuration
of 80 entries and 80 registers can achieve an energydelay-squared
(EDD) product of 0.952 without any loss
of performance and no increase in energy consumption.
The same configuration without compiler optimisations
has a EDD product of 1.078, losing 3% performance.
Furthermore, this scheme can be applied to a range of
baseline processors allowing designers to achieve EDD
products as low as 0.880 whilst still maintaining at least
the same performance and energy budget.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of the 2007 Workshop on the Interaction between Compilers and Computer Architecture (INTERACT'07) |
| Publication status | Published - 2007 |