Abstract / Description of output
DRAM latencies are inherently variable, potentially allowing a denial-of-service hardware Trojan (DoS HT) to degrade memory performance without becoming immediately obvious. This paper addresses the challenge of detecting a DoS HT that may have been inserted into a DRAM-based memory system, without requiring detailed internal knowledge of the DRAM device. We present a real-time machine-learning based DoS HT detection technique based on a low-cost hardware monitor at the interface to the DRAM controller, coupled with periodic software based analysis of monitoring output.
Original language | English |
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Title of host publication | Proceedings of the 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021) |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 6 |
ISBN (Electronic) | 978-1-7281-8281-0 |
ISBN (Print) | 978-1-7281-9493-6 |
DOIs | |
Publication status | Published - 10 Jan 2022 |
Event | 28th IEEE International Conference on Electronics Circuits and Systems - Dubai, United Arab Emirates Duration: 28 Nov 2021 → 1 Dec 2021 https://www.ieeeicecs2021.com/ |
Conference
Conference | 28th IEEE International Conference on Electronics Circuits and Systems |
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Abbreviated title | IEEE ICECS 2021 |
Country/Territory | United Arab Emirates |
City | Dubai |
Period | 28/11/21 → 1/12/21 |
Internet address |
Keywords / Materials (for Non-textual outputs)
- DRAM
- Hardware security
- Hardware Trojans
- Denial of service