Detecting denial-of-service hardware Trojans in DRAM-based memory systems

Heba Salem, Nigel Topham

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DRAM latencies are inherently variable, potentially allowing a denial-of-service hardware Trojan (DoS HT) to degrade memory performance without becoming immediately obvious. This paper addresses the challenge of detecting a DoS HT that may have been inserted into a DRAM-based memory system, without requiring detailed internal knowledge of the DRAM device. We present a real-time machine-learning based DoS HT detection technique based on a low-cost hardware monitor at the interface to the DRAM controller, coupled with periodic software based analysis of monitoring output.
Original languageEnglish
Title of host publicationProceedings of the 28th IEEE International Conference on Electronics Circuits and Systems (ICECS 2021)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages6
Publication statusAccepted/In press - 15 Sep 2021
Event28th IEEE International Conference on Electronics Circuits and Systems - Dubai, United Arab Emirates
Duration: 28 Nov 20211 Dec 2021
https://www.ieeeicecs2021.com/

Conference

Conference28th IEEE International Conference on Electronics Circuits and Systems
Abbreviated titleIEEE ICECS 2021
Country/TerritoryUnited Arab Emirates
CityDubai
Period28/11/211/12/21
Internet address

Keywords

  • DRAM
  • Hardware security
  • Hardware Trojans
  • Denial of service

Fingerprint

Dive into the research topics of 'Detecting denial-of-service hardware Trojans in DRAM-based memory systems'. Together they form a unique fingerprint.

Cite this