Die-Level Thinning for Flip-Chip Integration on Flexible Substrates

Muhammad Hassan Malik, Andreas Tsiamis, Hubert Zangl, Alfred Binder, Srinjoy Mitra, Ali Roshanghias

Research output: Contribution to journalArticlepeer-review


Die-level thinning, handling, and integration of singulated dies from multi-project wafers (MPW) are often used in research, early-stage development, and prototyping of flexible devices. There is a high demand for thin silicon devices for several applications, such as flexible electronics. To address this demand, we study a novel post-processing method on two silicon devices, an electrochemical impedance sensor, and Complementary Metal Oxide Semiconductor (CMOS) die. Both are drawn from an MPW batch, thinned at die-level after dicing and singulation down to 60 µm. The thinned dies were flip-chip bonded to flexible substrates and hermetically sealed by two techniques: thermosonic bonding of Au stud bumps and anisotropic conductive paste (ACP) bonding. The performance of the thinned dies was assessed via functional tests and compared to the original dies. Furthermore, the long-term reliability of the flip-chip bonded thinned sensors was demonstrated to be higher than the conventional wire-bonded sensors.
Original languageEnglish
Article number849
Issue number6
Early online date8 Mar 2022
Publication statusE-pub ahead of print - 8 Mar 2022


  • ultra-thin-chips
  • multi-project wafers
  • hybrid integration
  • thermoconic flip chip
  • anisotropic conductive adhesives
  • Flexible electronics
  • flip chip bonding


Dive into the research topics of 'Die-Level Thinning for Flip-Chip Integration on Flexible Substrates'. Together they form a unique fingerprint.

Cite this