Digital phase-sensitive detector (PSD) as accumulator-sampler and its implementation in FPGA

Hugh McCann, S Talha Ahsan

Research output: Contribution to journalArticlepeer-review


Phase-sensitive detection (PSD) is an established measurement technique for noisy signals. More recently, digital implementation of PSD using FPGA (Field Programmable Gate Array) or processor is becoming norm. This paper presents an FPGA-based digital PSD system, which is incorporated in a multi-channel bio-medical EIT instrument. In the paper, digital PSD has been analyzed using time- and frequency-domain methods of signal processing theory and a new interpretation of digital PSD in terms of accumulator-sampler has been given. Regarding design and implementation of the FPGA-based digital PSD system, two important issues of number of digitized waveform samples for use in PSD calculation and finite word length effect on PSD precision have been explored. Test results of the EIT instrument incorporating this digital PSD system have shown good noise performance, achieving an overall SNR of almost 80 dB at the high data-capturing rate of 100 frames/sec. The instrument also showed measurement capability to resolve large conductivity changes over very small spatial regions.
Original languageEnglish
Pages (from-to)65-73
Number of pages9
JournalScience International Lahore
Publication statusPublished - 2014


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