Distributed reorder buffer schemes for low power

G. Kucuk, O. Ergin, D. Ponomarev, K. Ghose

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We consider two approaches for reducing the complexity and power dissipation in processors that use separate register file to maintain committed register values. The first approach relies on a distributed implementation of the reorder buffer (ROB) that spreads the centralized ROB structure across the function units (FUs), with each distributed component sized to match the FU workload and with one write port and two read ports on each component. The second approach combines the use of the previously proposed retention latches and a distributed ROB implementation that uses minimally-ported distributed components. Such a combination avoids any read and write port conflicts on the distributed ROB components (with the exception of possible port conflicts in the course of commitment) and does not incur the associated performance degradation. Our designs are evaluated using the simulation of the SPEC 2000 benchmarks and SPICE simulations of the actual ROB layouts in 0.18 micron process. The ROB power savings of up to 49% can be realized with only 1.7% performance loss on the average.
Original languageEnglish
Title of host publicationComputer Design, 2003. Proceedings. 21st International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages364-370
Number of pages7
ISBN (Print)0-7695-2025-1
DOIs
Publication statusPublished - 1 Oct 2003

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