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Abstract / Description of output
A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29 µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615 nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15 dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼ 70 ps at 2 V excess bias and 773 nm showing no degradation to temporal resolution.
|Number of pages||4|
|Publication status||Published - 23 Jun 2019|
|Event||International Image Sensor Workshop - Snowbird Resort, Snowbird, United States|
Duration: 23 Jun 2019 → 27 Dec 2019
|Workshop||International Image Sensor Workshop|
|Period||23/06/19 → 27/12/19|
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1/10/13 → 31/03/19