Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel

Tarek Al Abbas; Danial Chitnis; Francesco Mattioli Della Rocca; Robert Henderson

Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel

Tarek Al Abbas, Danial Chitnis, Francesco Mattioli Della Rocca, Robert Henderson

School of Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract / Description of output

A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29 µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615 nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15 dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼ 70 ps at 2 V excess bias and 773 nm showing no degradation to temporal resolution.

Original language	English
Number of pages	4
Publication status	Published - 23 Jun 2019
Event	International Image Sensor Workshop - Snowbird Resort, Snowbird, United States Duration: 23 Jun 2019 → 27 Dec 2019 https://imagesensors.org/2019-international-image-sensor-workshop/

Workshop

Workshop	International Image Sensor Workshop
Abbreviated title	IISW
Country/Territory	United States
City	Snowbird
Period	23/06/19 → 27/12/19
Internet address	https://imagesensors.org/2019-international-image-sensor-workshop/

Access to Document

https://www.imagesensors.org/Past%20Workshops/2019%20Workshop/2019%20Papers/R20.pdf

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging
Henderson, R.
EPSRC
1/10/13 → 31/03/19
Project: Research

Cite this

@conference{69efa446c7a94006bf9701a20df50cf4,

title = "Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel",

abstract = "A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29 µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615 nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15 dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼ 70 ps at 2 V excess bias and 773 nm showing no degradation to temporal resolution. ",

author = "{Al Abbas}, Tarek and Danial Chitnis and {Mattioli Della Rocca}, Francesco and Robert Henderson",

year = "2019",

month = jun,

day = "23",

language = "English",

note = "International Image Sensor Workshop, IISW ; Conference date: 23-06-2019 Through 27-12-2019",

url = "https://imagesensors.org/2019-international-image-sensor-workshop/",

}

TY - CONF

T1 - Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel

AU - Al Abbas, Tarek

AU - Chitnis, Danial

AU - Mattioli Della Rocca, Francesco

AU - Henderson, Robert

PY - 2019/6/23

Y1 - 2019/6/23

N2 - A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29 µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615 nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15 dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼ 70 ps at 2 V excess bias and 773 nm showing no degradation to temporal resolution.

AB - A dual layer single photon avalanche diode (SPAD) pixel implemented in a 3D-stacked CMOS technology is presented. Two SPAD devices are arranged vertically such that the backside illuminated (BSI) top diode and the front side illuminated (FSI) bottom diode form a single pixel unit. The outputs of both 29 µm2 active area devices are connected to quench and processing electronic circuits on the bottom tier. Characterization results of both SPADs shows a peak photon detection probability (PDP) of 28% at 615 nm and 5% at 585nm for the top and bottom devices respectively at 3V excess bias. Dynamic range (DR) extension in single photon counting (SPC) mode by 15 dB and avoidance of pile-up conditions in time correlated single photon counting (TCSPC) mode are demonstrated. Angular response measurements of the pixel to incoming light are also presented. Both SPADs exhibit a low jitter of ∼ 70 ps at 2 V excess bias and 773 nm showing no degradation to temporal resolution.

M3 - Paper

T2 - International Image Sensor Workshop

Y2 - 23 June 2019 through 27 December 2019

ER -

Dual Layer 3D-Stacked High Dynamic Range SPAD Pixel

Abstract / Description of output

Workshop

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Projects

Multiplexed 'Touch and Tell' Optical Molecular Sensing and Imaging

Cite this