脉冲神经网络硬件互连系统的动态优先级仲裁策略

Translated title of the contribution: Dynamic priority arbitration strategy for interconnections of hardware Spiking Neural Networks

Jun Xiu Liu, Xing Yue Huang, Yu Ling Luo*, Yi Cao

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract

Based on the EMBRACE, i. e. a hardware architecture for the SNN, a dynamic priority arbitration strategy for a Networks-on-Chip (NoC) router is proposed to solve the non-balance traffic load problem of the SNN system. A2DmeshNoC system is used to provide the interconnected communication for the neurons. The dynamic priority arbitration strategy is based on the spiking transmission frequencies and it can reduce the risk of the packet loss and the average delay of the paths with heavy traffics, and improve the reliability of system. The Noxim simulator is used to build the simulation platform. The experimental results show that compared to the round-robin and fixed priority arbitration schemes, the proposed dynamic priority arbitration strategy has an average of 32.33% and 34.69%(maximum 84.86% and 86.20%) decrease for the delays of paths with heavy traffics. Based on the 90nm CMOS technology, the hardware area is 213, 471μm2, which demonstrates its scalability.

Translated title of the contributionDynamic priority arbitration strategy for interconnections of hardware Spiking Neural Networks
Original languageChinese
Pages (from-to)1898-1905
Number of pages8
JournalTien Tzu Hsueh Pao/Acta Electronica Sinica
Volume46
Issue number8
DOIs
Publication statusPublished - 1 Aug 2018

Keywords

  • arbiter
  • dynamic priority
  • networks-on-chip
  • router
  • Spiking Neural Networks

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