Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efﬁcient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2’s support for dynamic reconﬁgurability and show how the EDGE ISA facilities out-of-order vector execution.
|Title of host publication||1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies|
|Publication status||Published - 1 Jun 2010|