Dynamic Vectorization in the E2 Dynamic Multicore System

Andrew Putnam; Aaron Smith; Doug Burger

Dynamic Vectorization in the E2 Dynamic Multicore System

Andrew Putnam, Aaron Smith, Doug Burger

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efﬁcient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2’s support for dynamic reconﬁgurability and show how the EDGE ISA facilities out-of-order vector execution.

Original language	English
Title of host publication	1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies
Publication status	Published - 1 Jun 2010

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title = "Dynamic Vectorization in the E2 Dynamic Multicore System",

abstract = "Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efﬁcient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2{\textquoteright}s support for dynamic reconﬁgurability and show how the EDGE ISA facilities out-of-order vector execution.",

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year = "2010",

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T1 - Dynamic Vectorization in the E2 Dynamic Multicore System

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AU - Smith, Aaron

AU - Burger, Doug

PY - 2010/6/1

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N2 - Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efﬁcient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2’s support for dynamic reconﬁgurability and show how the EDGE ISA facilities out-of-order vector execution.

AB - Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efﬁcient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2’s support for dynamic reconﬁgurability and show how the EDGE ISA facilities out-of-order vector execution.

M3 - Conference contribution

BT - 1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies

ER -

Dynamic Vectorization in the E2 Dynamic Multicore System

Abstract

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