Dynamic Vectorization in the E2 Dynamic Multicore System

Andrew Putnam, Aaron Smith, Doug Burger

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Previous research has shown that Explicit Data Graph Execution (EDGE) instruction set architectures (ISA) allow for power efficient performance scaling. In this paper we describe the preliminary design of a new dynamic multicore processor called E2 that utilizes an EDGE ISA to allow for the dynamic composition of physical cores into logical processors. We provide details of E2’s support for dynamic reconfigurability and show how the EDGE ISA facilities out-of-order vector execution.
Original languageEnglish
Title of host publication1st International Workshop on Highly-efficient Accelerators and Reconfigurable Technologies
Publication statusPublished - 1 Jun 2010

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