Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Miles Gould; Harry Wagstaff; Bjoern Franke; Nigel Topham

doi:10.1145/2463209.2488760

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

Miles Gould, Harry Wagstaff, Bjoern Franke, Nigel Topham

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

Original language	English
Title of host publication	Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013
Publisher	ACM
ISBN (Print)	978-1-4503-2071-9
DOIs	https://doi.org/10.1145/2463209.2488760
Publication status	Published - 2013

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10.1145/2463209.2488760

http://dl.acm.org/citation.cfm?doid=2463209.2488760

Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors
Haas, H. (Principal Investigator), Franke, B. (Co-investigator), O'Boyle, M. (Co-investigator) & Topham, N. (Co-investigator)
EPSRC
1/11/10 → 30/07/14
Project: Research

Cite this

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title = "Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description",

abstract = "Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.",

author = "Miles Gould and Harry Wagstaff and Bjoern Franke and Nigel Topham",

year = "2013",

doi = "10.1145/2463209.2488760",

language = "English",

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booktitle = "Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013",

publisher = "ACM",

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Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description. / Gould, Miles; Wagstaff, Harry; Franke, Bjoern et al.
Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013. ACM, 2013. 21.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

AU - Gould, Miles

AU - Wagstaff, Harry

AU - Franke, Bjoern

AU - Topham, Nigel

PY - 2013

Y1 - 2013

N2 - Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

AB - Modern processor design tools integrate in their workflows generators for instruction set simulators (Iss) from architecture descriptions. Whilst these generated simulators are useful for design evaluation and software development, they suffer from poor performance. We present an ultra-fast Jit-compiled Iss generated from an ArchC description. We also introduce a novel partial evaluation optimisation, which further improves Jit compilation time and code quality. This results in a simulation rate of 510Mips for an Arm target across 45 Eembc and Spec benchmarks. On average, our Iss is 1.7 times faster than Simit-Arm, one of the fastest Iss generated from an architecture description.

U2 - 10.1145/2463209.2488760

DO - 10.1145/2463209.2488760

M3 - Conference contribution

SN - 978-1-4503-2071-9

BT - Publishing Proceedings of the 50th Annual Design Automation Conference - DAC 2013

PB - ACM

ER -

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description

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Dynamic Adaptation in Hetrogeneous Multicore Embedded Processors

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