Efficient Persist Barriers for Multicores

Arpit Joshi, Vijay Nagarajan, Marcelo Cintra, Stratis Viglas

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Emerging non-volatile memory technologies enable fast, fine-grained persistence compared to slow block-based devices. In order to ensure consistency of persistent state, dirty cache lines need to be periodically flushed from caches and made persistent in an order specified by the persistency model. A persist barrier is one mechanism for enforcing this ordering.

In this paper, we first show that current persist barrier implementations, owing to certain ordering dependencies, add cache line flushes to the critical path. Our main contribution is an efficient persist barrier, that reduces the number of cache line flushes happening in the critical path. We evaluate our proposed persist barrier by using it to enforce two persistency models: buffered epoch persistency with programmer inserted barriers; and buffered strict persistency in bulk mode with hardware inserted barriers. Experimental evaluations using micro-benchmarks (buffered epoch persistency) and multi-threaded workloads (buffered strict persistency) show that using our persist barrier improves performance by 22% and 20% respectively over the state-of the-art.
Original languageEnglish
Title of host publicationMICRO-48: Proceedings of the 48th International Symposium on Microarchitecture
PublisherAssociation for Computing Machinery (ACM)
Number of pages12
ISBN (Print)9781450340342
Publication statusPublished - 5 Dec 2015
EventThe 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015 - Waikiki, United States
Duration: 5 Dec 20159 Dec 2015


SymposiumThe 48th Annual IEEE/ACM International Symposium on Microarchitecture, 2015
Abbreviated titleMICRO-48
Country/TerritoryUnited States
Internet address


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