Eithne: A framework for benchmarking micro-core accelerators

Maurice Jamieson, Nicholas Brown

Research output: Contribution to conferencePosterpeer-review

Abstract / Description of output

Running existing HPC benchmarks as-is on micro-core architectures is at best difficult and most often impossible as they have a number of architectural features that makes them significantly different from traditional CPUs : tiny amounts on-chip RAM (c. 32KB), low-level knowledge specific to each device (including the host / device communications interface), limited communications bandwidth and complex or no device debugging environment. In order to compare and contrast different the micro-core architectures, a benchmark framework is required to abstract much of this complexity.

The modular Eithne framework supports the comparison of a number of micro-core architectures. The framework separates the actual benchmark from the details of how this is executed on the different technologies.

The framework was evaluated by running the LINPACK benchmark on the Adapteva Epiphany, PicoRV32 (RISC-V) and Orca soft-cores, NXP RV32M1, ARM Cortex-A9, and Xilinx MicroBlaze soft-core, and comparing resulting performance and power consumption.
Original languageEnglish
Number of pages2
Publication statusE-pub ahead of print - 21 Nov 2019
EventSupercomputing 2019 - Denver, United States
Duration: 17 Nov 201922 Nov 2019


ConferenceSupercomputing 2019
Abbreviated titleSC19
Country/TerritoryUnited States
Internet address


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