Electrical Assessment of Planarisation for CMP and SOG Technologies

J. P. Elliott; M. Fallon; A. J. Walton; J. T. M. Stevenson; A. O'Hara; C. M. Peyne; A. Shaffi; C. M. Reeves

Electrical Assessment of Planarisation for CMP and SOG Technologies

J. P. Elliott, M. Fallon, A. J. Walton, J. T. M. Stevenson, A. O'Hara, C. M. Peyne, A. Shaffi, C. M. Reeves

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	Undefined/Unknown
Title of host publication	IEEE International Conference on Microelectronic Test Structures
Pages	5
Number of pages	1
Publication status	Published - 1997

Cite this

@inproceedings{ae447344e7794e76a6a341e60c65ae39,

title = "Electrical Assessment of Planarisation for CMP and SOG Technologies",

author = "Elliott, \{J. P.\} and M. Fallon and Walton, \{A. J.\} and Stevenson, \{J. T. M.\} and A. O'Hara and Peyne, \{C. M.\} and A. Shaffi and Reeves, \{C. M.\}",

year = "1997",

language = "Undefined/Unknown",

pages = "5",

booktitle = "IEEE International Conference on Microelectronic Test Structures",

}