Enabling Unrestricted Automated Synthesis of Portable Hardware Accelerators for Virtual Machines

Miljan Vuleti, Christophe Dubach, Laura Pozzi, Paolo Ienne

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The performance of virtual machines (e.g., Java Virtual Machines---JVMs) can be significantly improved when critical code sections (e.g., Java bytecode methods) are migrated from software to reconfigurable hardware. In contrast to the compile-once-run-anywhere concept of virtual machines, reconfigurable applications lack portability and transparent SW/HW interfacing: applicability of accelerated hardware solutions is often limited to a single platform. In this work, we apply a virtualisation layer that provides portable and seamless integration of hardware and software components to a Java Virtual Machine platform, making it capable of accelerating any Java bytecode method by using platform-independent hardware accelerators. The virtualisation layer not only improves portability of accelerated Java bytecode applications, but also supports runtime optimisations and enables unrestricted automated synthesis of arbitrary Java bytecode to hardware. To show the advantages and measure the limited overheads of our approach, we run several accelerated applications (handwritten and synthesised) on a real embedded platform. We also show our synthesis flow and discuss its advanced features fostered by the virtualisation layer.
Original languageEnglish
Title of host publicationCODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Place of PublicationNew York, NY, USA
PublisherACM
Pages243-248
Number of pages6
ISBN (Print)1-59593-161-9
DOIs
Publication statusPublished - 2005

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