Expanding the un-usable area strategy for improved utilization of reconfigurable FPGAS

Godwin Enemali, Adewale Adetomi, Tughrul Arslan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The addition of hard blocks such as Block RAMs and Digital Signal Processors, have proven to be good means of improving various performance metrics in FPGAS. This however places stricter constraints on runtime relocation of hardware tasks and hence reduces their application in dealing with permanent faults. In this paper, we present a strategy that enhances the utilization of heterogeneous reconfigurable FPGAS by minimizing resources which are tied down as unusable areas. Our results show that the strategy leads to a 9.4% reduction in task rejections and improved placement quality compared to state of the art techniques. The complete implementation occupies only 1712 LUTs and 1645 Flip Flops on the Xilinx's xc7z100ffg900-2. Based on this strategy, more task relocations can be obtained which enhances the capacity of FPGAS to deal with permanent faults.

Original languageEnglish
Title of host publication2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages139-144
Number of pages6
ISBN (Electronic)9781538634394
DOIs
Publication statusPublished - 19 Sep 2017
Event2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017 - Pasadena, United States
Duration: 24 Jul 201727 Jul 2017

Publication series

Name2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017

Conference

Conference2017 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2017
Country/TerritoryUnited States
CityPasadena
Period24/07/1727/07/17

Keywords

  • allocation
  • design optimization
  • FPGA
  • heterogenous platform
  • runtime placement

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