Exploring the Suitability of the Cerebras Wafer Scale Engine for Stencil-Based Computation Codes

Nick Brown, Brandon Echols, Justs Zarins, Tobias Grosser

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

The Cerebras Wafer Scale Engine (WSE) is an accelerator that combines hundreds of thousands of AI-cores onto a single chip. Whilst this technology has been designed for machine learning workloads, the significant amount of available raw compute means that it is also a very interesting potential target for accelerating traditional HPC computational codes. Many of these algorithms are stencil-based, where update operations involve contributions from neighbouring elements, and in this paper we explore the suitability of this technology for such codes from the perspective of an early adopter of the technology, compared to CPUs and GPUs. Using TensorFlow as the interface, we explore the performance and demonstrate that, whilst there is still work to be done around exposing the programming interface to users, performance of the WSE is impressive as it out performs four V100 GPUs by two and a half times and two Intel Xeon Platinum CPUs by around 114 times in our experiments. There is significant potential therefore for this technology to play an important role in accelerating HPC codes on future exascale supercomputers.
Original languageEnglish
Title of host publicationEuro-Par 2022: Parallel Processing Workshops. Euro-Par 2022. Lecture Notes in Computer Science
Number of pages14
ISBN (Electronic)9783031312090
ISBN (Print)9783031312083
Publication statusPublished - 2 May 2023
EventInternational workshop on DSLs for HPC - Hugh Fraser room, Glasgow, United Kingdom
Duration: 22 Aug 202222 Aug 2022

Publication series

NameLecture Notes in Computer Science
ISSN (Print)0302-9743
ISSN (Electronic)1611-3349


WorkshopInternational workshop on DSLs for HPC
Abbreviated titleDSL-HPC
Country/TerritoryUnited Kingdom
Internet address


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