Exploring the Versal AI engines for accelerating stencil-based atmospheric advection simulation

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

AMD Xilinx's new Versal Adaptive Compute Acceleration Platform (ACAP) is an FPGA architecture combining reconfigurable fabric with other on-chip hardened compute resources. AI engines are one of these and, by operating in a highly vectorized manner, they provide significant raw compute that is potentially beneficial for a range of workloads including HPC simulation. However, this technology is still early-on, and as yet unproven for accelerating HPC codes, with a lack of benchmarking and best practice.

This paper presents an experience report, exploring porting of the Piacsek and Williams (PW) advection scheme onto the Versal ACAP, using the chip's AI engines to accelerate the compute. A stencil-based algorithm, advection is commonplace in atmospheric modelling, including several Met Office codes who initially developed this scheme. Using this algorithm as a vehicle, we explore optimal approaches for structuring AI engine compute kernels and how best to interface the AI engines with programmable logic. Evaluating performance using a VCK5000 against non-AI engine FPGA configurations on the VCK5000 and Alveo U280, as well as a 24-core Xeon Platinum Cascade Lake CPU and Nvidia V100 GPU, we found that whilst the number of channels between the fabric and AI engines are a limitation, by leveraging the ACAP we can double performance compared to an Alveo U280.
Original languageEnglish
Title of host publicationProceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
PublisherAssociation for Computing Machinery (ACM)
DOIs
Publication statusPublished - 12 Feb 2023
EventACM/SIGDA International Symposium on Field-Programmable Gate Arrays - Monterey, United States
Duration: 12 Feb 202314 Feb 2023
https://www.isfpga.org/

Conference

ConferenceACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Abbreviated titleFPGA
Country/TerritoryUnited States
CityMonterey
Period12/02/2314/02/23
Internet address

Keywords / Materials (for Non-textual outputs)

  • Versal ACAP
  • AI engines
  • FPGAs
  • stencil based algorithms
  • VCK5000
  • atmospheric advection
  • HPC

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  • FPGA Testbed

    Jackson, A. & Brown, N.

    STFC

    1/04/2130/09/22

    Project: Research

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