Express Cube Topologies for on-Chip Interconnects

B. Grot, J. Hestness, S.W. Keckler, O. Mutlu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Driven by continuing scaling of Moore's law, chip multi-processors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. Scalability of on-chip interconnect topologies is critical to meeting these demands. In this work, we seek to develop a better understanding of how network topologies scale with regard to cost, performance, and energy considering the advantages and limitations afforded on a die. Our contributions are three-fold. First, we propose a new topology, called Multidrop Express Channels (MECS), that uses a one-to-many communication model enabling a high degree of connectivity in a bandwidth-efficient manner. In a 64-terminal network, MECS enjoys a 9% latency advantage over other topologies at low network loads, which extends to over 20% in a 256-terminal network. Second, we demonstrate that partitioning the available wires among multiple networks and channels enables new opportunities for trading-off performance, area, and energy-efficiency that depend on the partitioning scheme. Third, we introduce Generalized Express Cubes - a framework for expressing the space of on-chip interconnects - and demonstrate how existing and proposed topologies can be mapped to it.
Original languageEnglish
Title of host publicationHigh Performance Computer Architecture, 2009. HPCA 2009. IEEE 15th International Symposium on
Number of pages12
Publication statusPublished - 2009

Keywords / Materials (for Non-textual outputs)

  • hypercube networks
  • system-on-chip
  • express cube topologies
  • generalized express cubes
  • multidrop express channels
  • multiple networks
  • network topologies
  • on-chip interconnect topologies
  • onchip interconnects
  • systems-on-a-chip
  • Costs
  • Delay
  • Energy efficiency
  • Moore's Law
  • Network topology
  • Network-on-a-chip
  • Scalability
  • Silicon
  • System-on-a-chip
  • Wires


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