Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers

Amna Shahab, Mingcan Zhu, Artemiy Margaritov, Boris Grot

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

The slowdown in technology scaling mandates rethinking of conventional CPU architectures in a quest for higher performance and new capabilities. This work takes a step in this direction by questioning the value of on-chip shared last level caches (LLCs) in server processors and argues for a better alternative. Shared LLCs have a number of limitations, including on-chip area constraints that limit storage capacity, long planar interconnect spans that increase access latency, and contention for the shared cache capacity that hurts performance under workload colocation.
To overcome these limitations, we propose a Die-Stacked Private LLC Organization (SILO), which combines conventional on-chip private L1 (and optionally, L2) caches with a per-core private LLC in die-stacked DRAM. By stacking LLC slices directly above each core, SILO avoids long planar wire spans. The use of private caches inherently avoids inter-core cache contention. Last but not the least, engineering the DRAM for latency affords low access delays while still providing over 100MB of capacity per core in today’s technology. Evaluation results show that SILO outperforms state-of-the-art conventional cache architectures on a range of scale-out and traditional workloads while delivering strong performance isolation under colocation.
Original languageEnglish
Title of host publication2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)
Place of PublicationFukuoka City, Japan
PublisherInstitute of Electrical and Electronics Engineers
Pages559-572
Number of pages14
ISBN (Electronic)978-1-5386-6240-3
ISBN (Print)978-1-5386-6241-0
DOIs
Publication statusPublished - 13 Dec 2018
Event51st Annual IEEE/ACM International Symposium on Microarchitecture - Fukuoka City, Japan
Duration: 20 Oct 201824 Oct 2018
https://www.microarch.org/micro51/

Conference

Conference51st Annual IEEE/ACM International Symposium on Microarchitecture
Abbreviated titleMICRO 51
Country/TerritoryJapan
CityFukuoka City
Period20/10/1824/10/18
Internet address

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