Abstract / Description of output
The slowdown in technology scaling mandates rethinking of conventional CPU architectures in a quest for higher performance and new capabilities. This work takes a step in this direction by questioning the value of on-chip shared last level caches (LLCs) in server processors and argues for a better alternative. Shared LLCs have a number of limitations, including on-chip area constraints that limit storage capacity, long planar interconnect spans that increase access latency, and contention for the shared cache capacity that hurts performance under workload colocation.
To overcome these limitations, we propose a Die-Stacked Private LLC Organization (SILO), which combines conventional on-chip private L1 (and optionally, L2) caches with a per-core private LLC in die-stacked DRAM. By stacking LLC slices directly above each core, SILO avoids long planar wire spans. The use of private caches inherently avoids inter-core cache contention. Last but not the least, engineering the DRAM for latency affords low access delays while still providing over 100MB of capacity per core in today’s technology. Evaluation results show that SILO outperforms state-of-the-art conventional cache architectures on a range of scale-out and traditional workloads while delivering strong performance isolation under colocation.
To overcome these limitations, we propose a Die-Stacked Private LLC Organization (SILO), which combines conventional on-chip private L1 (and optionally, L2) caches with a per-core private LLC in die-stacked DRAM. By stacking LLC slices directly above each core, SILO avoids long planar wire spans. The use of private caches inherently avoids inter-core cache contention. Last but not the least, engineering the DRAM for latency affords low access delays while still providing over 100MB of capacity per core in today’s technology. Evaluation results show that SILO outperforms state-of-the-art conventional cache architectures on a range of scale-out and traditional workloads while delivering strong performance isolation under colocation.
Original language | English |
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Title of host publication | 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) |
Place of Publication | Fukuoka City, Japan |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 559-572 |
Number of pages | 14 |
ISBN (Electronic) | 978-1-5386-6240-3 |
ISBN (Print) | 978-1-5386-6241-0 |
DOIs | |
Publication status | Published - 13 Dec 2018 |
Event | 51st Annual IEEE/ACM International Symposium on Microarchitecture - Fukuoka City, Japan Duration: 20 Oct 2018 → 24 Oct 2018 https://www.microarch.org/micro51/ |
Conference
Conference | 51st Annual IEEE/ACM International Symposium on Microarchitecture |
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Abbreviated title | MICRO 51 |
Country/Territory | Japan |
City | Fukuoka City |
Period | 20/10/18 → 24/10/18 |
Internet address |
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Boris Grot
- School of Informatics - Personal Chair of Computer Systems and Architecture
- Institute for Computing Systems Architecture
- Computer Systems
Person: Academic: Research Active