@inproceedings{2f0aa61e6bfb46ef8477a5075ec409af,
title = "Fast modulo 2n−1 and 2n;1 adder using carry-chain on FPGA",
abstract = "Modular addition is a widely used operation in Residue Number System applications. Specific sets of moduli allow fast RNS operations such as binary conversions and multiplications. Most of them use modulo 2n - 1 and 2n + 1 additions. This paper presents four fast and small architectures for these specific moduli targeting modern FPGAs with fast carry chains. The use of this arithmetic dedicated feature allows fast and small modular adders. Our modulo 2n - 1 adders have a single zero representation. Our modulo 2n+1 adders are designed for binary and diminished-one representation with and without zero value management.",
keywords = "Modular adder, carry-chain, FPGA, RNS, 2n−1 and 2n + 1 moduli",
author = "Laurent-St{\'e}phane Didier and Luc Jaulmes",
year = "2014",
month = may,
day = "8",
doi = "10.1109/ACSSC.2013.6810475",
language = "English",
series = "Asilomar Conference on Signals, Systems & Computers",
publisher = "Institute of Electrical and Electronics Engineers",
pages = "1155--1159",
editor = "Matthews, {Michael B.}",
booktitle = "2013 Asilomar Conference on Signals, Systems and Computers",
address = "United States",
note = "2013 Asilomar Conference on Signals, Systems, and Computers, Asilomar 2013 ; Conference date: 03-11-2013 Through 06-11-2013",
}