Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs

Adewale Adetomi; Godwin Enemali; Tughrul Arslan

doi:10.1109/AHS.2018.8541470

Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs

Adewale Adetomi, Godwin Enemali, Tughrul Arslan

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fault tolerance has become more important in modern chips. This is because of the increasing use of smaller process nodes. Though there has been a tremendous increase in the integrating density of transistors, the miniaturized size has made them more vulnerable to ageing-and radiation-induced hard errors. In this paper, we present mechanisms for tackling soft and hard errors in CERANoC, a Clock-Enabled Relocation-Aware Network-on-Chip. It has been developed as a communication network that facilitates the online relocation of circuits in response to hard errors. This highlights why it is important that the network itself is resilient to errors.

Original language	English
Title of host publication	2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018)
Publisher	IEEE PES
Pages	214-217
Number of pages	4
ISBN (Electronic)	978-1-5386-7753-7
DOIs	https://doi.org/10.1109/AHS.2018.8541470
Publication status	Published - 22 Nov 2018
Event	NASA/ESA Conference on Adaptive Hardware and Systems (AHS) - Edinburgh Duration: 6 Aug 2018 → 9 Aug 2018

Publication series

Name	NASA/ESA Conference on Adaptive Hardware and Systems
Publisher	IEEE
ISSN (Print)	1939-7003

Conference

Conference	NASA/ESA Conference on Adaptive Hardware and Systems (AHS)
City	Edinburgh
Period	6/08/18 → 9/08/18

Keywords

FPGA
CELOC
CERANoC
clock buffers
dynamic communication
network on chip
reliability
relocation

Access to Document

10.1109/AHS.2018.8541470

Cite this

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title = "Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs",

abstract = "Fault tolerance has become more important in modern chips. This is because of the increasing use of smaller process nodes. Though there has been a tremendous increase in the integrating density of transistors, the miniaturized size has made them more vulnerable to ageing-and radiation-induced hard errors. In this paper, we present mechanisms for tackling soft and hard errors in CERANoC, a Clock-Enabled Relocation-Aware Network-on-Chip. It has been developed as a communication network that facilitates the online relocation of circuits in response to hard errors. This highlights why it is important that the network itself is resilient to errors.",

keywords = "FPGA, CELOC, CERANoC, clock buffers, dynamic communication, network on chip, reliability, relocation",

author = "Adewale Adetomi and Godwin Enemali and Tughrul Arslan",

note = "Acceptance date set to exclude from REF OA Policy ; NASA/ESA Conference on Adaptive Hardware and Systems (AHS) ; Conference date: 06-08-2018 Through 09-08-2018",

year = "2018",

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doi = "10.1109/AHS.2018.8541470",

language = "English",

series = "NASA/ESA Conference on Adaptive Hardware and Systems",

publisher = "IEEE PES",

pages = "214--217",

booktitle = "2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018)",

}

Adetomi, A, Enemali, G & Arslan, T 2018, Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs. in 2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018). NASA/ESA Conference on Adaptive Hardware and Systems, IEEE PES, pp. 214-217, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), Edinburgh, 6/08/18. https://doi.org/10.1109/AHS.2018.8541470

Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs. / Adetomi, Adewale; Enemali, Godwin ; Arslan, Tughrul.

2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018). IEEE PES, 2018. p. 214-217 (NASA/ESA Conference on Adaptive Hardware and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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