Fault-Tolerant Mechanisms for Relocation-Aware Dynamic On-Chip Communication on FPGAs

Adewale Adetomi*, Godwin Enemali, Tughrul Arslan

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Fault tolerance has become more important in modern chips. This is because of the increasing use of smaller process nodes. Though there has been a tremendous increase in the integrating density of transistors, the miniaturized size has made them more vulnerable to ageing-and radiation-induced hard errors. In this paper, we present mechanisms for tackling soft and hard errors in CERANoC, a Clock-Enabled Relocation-Aware Network-on-Chip. It has been developed as a communication network that facilitates the online relocation of circuits in response to hard errors. This highlights why it is important that the network itself is resilient to errors.

Original languageEnglish
Title of host publication2018 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS (AHS 2018)
PublisherIEEE PES
Pages214-217
Number of pages4
ISBN (Electronic)978-1-5386-7753-7
DOIs
Publication statusPublished - 22 Nov 2018
EventNASA/ESA Conference on Adaptive Hardware and Systems (AHS) - Edinburgh
Duration: 6 Aug 20189 Aug 2018

Publication series

NameNASA/ESA Conference on Adaptive Hardware and Systems
PublisherIEEE
ISSN (Print)1939-7003

Conference

ConferenceNASA/ESA Conference on Adaptive Hardware and Systems (AHS)
CityEdinburgh
Period6/08/189/08/18

Keywords / Materials (for Non-textual outputs)

  • FPGA
  • CELOC
  • CERANoC
  • clock buffers
  • dynamic communication
  • network on chip
  • reliability
  • relocation

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