Flowblaze: Stateful Packet Processing in Hardware

Salvatore Pontarelli, Roberto Bifulco, Marco Bonola, Carmelo Cascone, Marco Spaziani, Valerio Bruschi, Davide Sanvito, Giuseppe Siracusano, Antonio Capone, Michio Honda, Felipe Huici, Giuseppe Bianchi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

While programmable NICs allow for better scalability to handle growing network workloads, providing an expressive yet simple abstraction to program stateful network functions in hardware remains a research challenge. We address the problem with FlowBlaze, an open abstraction for building stateful packet processing functions in hardware. The abstraction is based on Extended Finite State Machines and introduces the explicit definition of flow state, allowing Flow-Blaze to leverage flow-level parallelism. FlowBlaze is expressive, supporting a wide range of complex network functions, and easy to use, hiding low-level hardware implementation issues from the programmer. Our implementation of FlowBlaze on a NetFPGA SmartNIC achieves very low latency (in the order of a few microseconds), consumes relatively little power, can hold per-flow state for hundreds of thousands of flows, and yields speeds of 40 Gb/s, allowing for even higher speeds on newer FPGA models. Both hardware and software implementations of FlowBlaze are publicly available.
Original languageEnglish
Title of host publicationProceedings of the 16th USENIX Conference on Networked Systems Design and Implementation
Place of PublicationUSA
PublisherUSENIX Association
Number of pages17
ISBN (Print)9781931971492
Publication statusPublished - 26 Feb 2019
Event16th USENIX Conference on Networked Systems Design and Implementation - Boston, United States
Duration: 26 Feb 201928 Feb 2019
Conference number: 16


Conference16th USENIX Conference on Networked Systems Design and Implementation
Abbreviated titleNSDI 2019
Country/TerritoryUnited States
Internet address


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