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Abstract / Description of output
In recent years the use of FPGAs to accelerate scientific applications has grown, with numerous applications demonstrating the benefit of FPGAs for high performance workloads. However, whilst High Level Synthesis (HLS) has significantly lowered the barrier to entry in programming FPGAs by enabling programmers to use C++, a major challenge is that most often these codes are not originally written in C++. Instead, Fortran is the lingua franca of scientific computing and-so it requires a complex and time consuming initial step to convert into C++ even before considering the FPGA.
In this paper we describe work enabling Fortran for AMD Xilinx FPGAs by connecting the LLVM Flang front end to AMD Xilinx's LLVM back end. This enables programmers to use Fortran as a first-class language for programming FPGAs, and as we demonstrate enjoy all the tuning and optimisation opportunities that HLS C++ provides. Furthermore, we demonstrate that certain language features of Fortran make it especially beneficial for programming FPGAs compared to C++. The result of this work is a lowering of the barrier to entry in using FPGAs for scientific computing, enabling programmers to leverage their existing codebase and language of choice on the FPGA directly.
In this paper we describe work enabling Fortran for AMD Xilinx FPGAs by connecting the LLVM Flang front end to AMD Xilinx's LLVM back end. This enables programmers to use Fortran as a first-class language for programming FPGAs, and as we demonstrate enjoy all the tuning and optimisation opportunities that HLS C++ provides. Furthermore, we demonstrate that certain language features of Fortran make it especially beneficial for programming FPGAs compared to C++. The result of this work is a lowering of the barrier to entry in using FPGAs for scientific computing, enabling programmers to leverage their existing codebase and language of choice on the FPGA directly.
Original language | English |
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Title of host publication | Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications |
Publisher | IEEE Computer Society Press |
Pages | 10-18 |
DOIs | |
Publication status | Accepted/In press - 1 Jul 2023 |
Event | 33rd International Conference on Field-Programmable Logic and Applications - Gothenburg, Sweden Duration: 4 Sept 2023 → 8 Sept 2023 https://2023.fpl.org/home |
Conference
Conference | 33rd International Conference on Field-Programmable Logic and Applications |
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Abbreviated title | FPL 2023 |
Country/Territory | Sweden |
City | Gothenburg |
Period | 4/09/23 → 8/09/23 |
Internet address |
Keywords / Materials (for Non-textual outputs)
- FPGAs
- Fortran
- High Level Synthesis
- HPC
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