Fortran High-Level Synthesis: Reducing the barriers to accelerating HPC codes on FPGAs

Gabriel Rodríguez Canal*, Nick Brown, Tim Dykes, Jessica Jones, Utz-Uwe Haus

*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

In recent years the use of FPGAs to accelerate scientific applications has grown, with numerous applications demonstrating the benefit of FPGAs for high performance workloads. However, whilst High Level Synthesis (HLS) has significantly lowered the barrier to entry in programming FPGAs by enabling programmers to use C++, a major challenge is that most often these codes are not originally written in C++. Instead, Fortran is the lingua franca of scientific computing and-so it requires a complex and time consuming initial step to convert into C++ even before considering the FPGA.

In this paper we describe work enabling Fortran for AMD Xilinx FPGAs by connecting the LLVM Flang front end to AMD Xilinx's LLVM back end. This enables programmers to use Fortran as a first-class language for programming FPGAs, and as we demonstrate enjoy all the tuning and optimisation opportunities that HLS C++ provides. Furthermore, we demonstrate that certain language features of Fortran make it especially beneficial for programming FPGAs compared to C++. The result of this work is a lowering of the barrier to entry in using FPGAs for scientific computing, enabling programmers to leverage their existing codebase and language of choice on the FPGA directly.
Original languageEnglish
Title of host publicationProceedings of the 33rd International Conference on Field-Programmable Logic and Applications
PublisherIEEE Computer Society Press
Pages10-18
DOIs
Publication statusAccepted/In press - 1 Jul 2023
Event33rd International Conference on Field-Programmable Logic and Applications - Gothenburg, Sweden
Duration: 4 Sept 20238 Sept 2023
https://2023.fpl.org/home

Conference

Conference33rd International Conference on Field-Programmable Logic and Applications
Abbreviated titleFPL 2023
Country/TerritorySweden
CityGothenburg
Period4/09/238/09/23
Internet address

Keywords / Materials (for Non-textual outputs)

  • FPGAs
  • Fortran
  • High Level Synthesis
  • HPC

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