FPGA design of fixed-complexity high-throughput MIMO detector based on QRDM algorithm

Xiang Wu, J.S. Thompson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

This paper presents a field-programmable gate array (FPGA) implementation of an unbiased minimum mean square error (MMSE) metric based QR-decomposition M (QRDM) algorithm for the multiple-input multiple-output (MIMO) systems. Two advanced techniques, namely the merge-sort (MS) based and winner path expansion (WPE) based sorting schemes have been implemented and validated on an FPGA platform for a 4 #x00D7;4 16-QAM MIMO system. The results show that the MS-QRDM is advantageous in the simplified control circuits and leads to less logic resource use, whereas the WPE-QRDM is able to achieve the minimum use of the computational units and results in fewer multipliers. Furthermore, it also shows that both schemes can support up to 1.6 Gbps decoding throughput when they are implemented in a fully pipelined parallel architecture.
Original languageUndefined/Unknown
Title of host publicationCommunications and Networking in China (CHINACOM), 2010 5th International ICST Conference on
Pages1 -4
Publication statusPublished - 1 Aug 2010

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