FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array

D. -U Li, R. Walker, A. Buts, Robert Henderson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32times32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems (ISCAS)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages3082 - 3085
ISBN (Print)978-1-4244-3827-3
DOIs
Publication statusPublished - 1 May 2009
EventIEEE International Symposium on Circuits and Systems (ISCAS) - Taipei, Taiwan, Province of China
Duration: 24 May 200927 May 2009

Conference

ConferenceIEEE International Symposium on Circuits and Systems (ISCAS)
CountryTaiwan, Province of China
CityTaipei
Period24/05/0927/05/09

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