FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS   Single-Photon Avalanche Diode Array

D. -U Li; R. Walker; A. Buts; Robert Henderson

doi:10.1109/ISCAS.2009.5118454

FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array

D. -U Li, R. Walker, A. Buts, Robert Henderson

School of Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32times32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and Systems (ISCAS)
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	3082 - 3085
ISBN (Print)	978-1-4244-3827-3
DOIs	https://doi.org/10.1109/ISCAS.2009.5118454
Publication status	Published - 1 May 2009
Event	IEEE International Symposium on Circuits and Systems (ISCAS) - Taipei, Taiwan, Province of China Duration: 24 May 2009 → 27 May 2009

Conference

Conference	IEEE International Symposium on Circuits and Systems (ISCAS)
Country/Territory	Taiwan, Province of China
City	Taipei
Period	24/05/09 → 27/05/09

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10.1109/ISCAS.2009.5118454

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Li, D. -U., Walker, R., Buts, A., & Henderson, R. (2009). FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array. In IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 3082 - 3085). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ISCAS.2009.5118454

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abstract = "A new integration based fluorescence lifetime imaging microscopy (FLIM) called IEM has been proposed to implement lifetime calculations. A real-time hardware implementation of this IEM FLIM algorithm suitable for a single photon avalanche diode (SPAD) array in 0.13 mum CMOS technology is now implemented on FPGA. A widefield microscope was adapted to accommodate the array and test it on biological applications. Video-rate fluorescence lifetime imaging has been achieved, by performing parallel 32times32 lifetime calculations, realizing the first, compact, and low-cost FLIM camera.",

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Li, D-U, Walker, R, Buts, A & Henderson, R 2009, FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array. in IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers (IEEE), pp. 3082 - 3085, IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, Province of China, 24/05/09. https://doi.org/10.1109/ISCAS.2009.5118454

FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array. / Li, D. -U; Walker, R.; Buts, A. et al.

IEEE International Symposium on Circuits and Systems (ISCAS). Institute of Electrical and Electronics Engineers (IEEE), 2009. p. 3082 - 3085.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T2 - IEEE International Symposium on Circuits and Systems (ISCAS)

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ER -

FPGA Implementation of a Video-rate Fluorescence Lifetime Imaging System with a 32×32 CMOS Single-Photon Avalanche Diode Array

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