Scientists and engineers are continually demanding the ability to generate more detailed results at reduced time to solution. Little wonder then that, in an attempt to meet such ambition, the future role that novel hardware architectures such as Field Programmable Gate Arrays (FPGAs) can play in High Performance Computing (HPC) is of great interest. In this whitepaper we argue that there are four major benefits that FPGAs can provide to HPC workloads and describe the importance of designing HPC codes from the perspective of dataflow for FPGAs. We describe three rules for achieving good performance for HPC codes on the FPGA, determining whether a general design approach will deliver acceptable performance before designing top down and then optimising bottom up.The result of this whitepaper is an understanding of where FPGAs can benefit HPC workloads and a design methodology for developing high performance dataflow codes more widely.
|Number of pages||13|
|Publication status||Published - 20 May 2022|