Fuse: A Technique to Anticipate Failures due to Degradation in ALUs

Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes the fuse, a technique to anticipate failures due to degradation in any ALU (Arithmetic Logic Unit), and particularly in an adder. The fuse consists of a replica of the weakest transistor in the adder and the circuitry required to measure its degradation. By mimicking the behavior of the replicated transistor the fuse anticipates the failure short before the first failure in the adder appears, and hence, data corruption and program crashes can be avoided. Our results show that the fuse anticipates the failure in more than 99.9% of the cases after 96.6% of the lifetime, even for pessimistic random within-die variations.
Original languageEnglish
Title of host publication13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages15-22
Number of pages8
ISBN (Print)0-7695-2918-6
DOIs
Publication statusPublished - 2007

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