Abstract / Description of output
This brief presents an efficient implementation of JPEG2000 encoding algorithm based on an architecture consisting of a coarse-grained dynamically reconfigurable instruction cell array and an embedded advanced RISC machine core. In this implementation, different tasks within the JPEG2000 encoding algorithm are allocated with proper computational resources to achieve high throughput. The proposed architecture is dynamically reconfigured for different tasks during the encoding process. Simulation results demonstrate that the proposed architecture provides a throughput of up to 52.1 f/s (or 19.18 ms/frame) to encode a 256 × 256 standard Lena test image. Compared with various digital signal processor & very long instruction word-based JPEG2000 solutions, the proposed architecture provides significant advantages in terms of throughput and energy consumption.
Original language | English |
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Pages (from-to) | 2343 - 2348 |
Number of pages | 6 |
Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Volume | 21 |
Issue number | 12 |
DOIs | |
Publication status | Published - 2013 |
Keywords / Materials (for Non-textual outputs)
- image coding
- reconfigurable architectures
- reduced instruction set computing
- JPEG2000 encoding algorithm
- Lena test image
- coarse-grained dynamically reconfigurable instruction cell array
- coarse-grained dynamically reconfigurable architecture
- computational resource allocation
- digital signal processor
- embedded advanced RISC machine core
- energy consumption
- very long instruction word-based JPEG2000 solutions
- Image processing
- parallel architecture
- computer architecture
- Discrete wavelet transforms
- Encoding
- Kernel
- Multiplexing
- Throughput
- transform coding