High-efficiency high voltage hybrid charge pump design with an improved chip area

Bartas Abaravicius, Sandy Cochran, Srinjoy Mitra

Research output: Contribution to journalArticlepeer-review


A hybrid charge pump was developed in a 0.13-μm Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of zero-reversion loss cross-coupled stages and a new, self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.
Original languageEnglish
Pages (from-to)1-12
Number of pages12
JournalIEEE Access
Early online date23 Jun 2021
Publication statusE-pub ahead of print - 23 Jun 2021


  • Charge pump
  • high-voltage
  • hybrid
  • BCD
  • small-area
  • cross-coupled
  • serial-parallel


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