HW/SW Co-designed Processors: Challenges, Design Choices and a Simulation Infrastructure for Evaluation

Rakesh Kumar, Jose Cano Reyes, Demos Pavlou, Kyriakos Stavrou, Enric Gibert, Alejandro Martinez, Antonio González

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Improving single thread performance is a key challenge in modern microprocessors especially because the traditional approach of increasing clock frequency and deep pipelining cannot be pushed further due to power constraints. Therefore, researchers have been looking at unconventional architectures to boost single thread performance without running into the
power wall. HW/SW co-designed processors like Nvidia Denver, are emerging as a promising alternative.
However, HW/SW co-designed processors need to address some key challenges such as startup delay, providing high performance with simple hardware, translation/optimization overhead, etc. before they can become mainstream. A fundamental requirement for evaluating different design choices and trade-offs
to meet these challenges is to have a simulation infrastructure. Unfortunately, there is no such infrastructure available today. Building the aforementioned infrastructure itself poses significant challenges as it encompasses the complexities of not only an architectural framework but also of a compilation one.
This paper identifies the key challenges that HW/SW codesigned processors face and the basic requirements for a simulation infrastructure targeting these architectures. Furthermore, the paper presents DARCO, a simulation infrastructure to enable research in this domain.
Original languageEnglish
Title of host publicationThe IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2017)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages185-194
Number of pages10
ISBN (Electronic) 978-1-5386-3890-3
DOIs
Publication statusPublished - 13 Jul 2017
Event2017 IEEE International Symposium on Performance Analysis of Systems and Software - Santa Rosa, United States
Duration: 24 Apr 201725 Apr 2017
http://www.ispass.org/ispass2017/

Conference

Conference2017 IEEE International Symposium on Performance Analysis of Systems and Software
Abbreviated titleISPASS 2017
Country/TerritoryUnited States
CitySanta Rosa
Period24/04/1725/04/17
Internet address

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