Hybrid CMOS/Memristor Circuit Design Methodology

Sachin Maheshwari; Spyros  Stathopoulos; Jiaqi Wang; Alex Serb; Yihan Pan; Andrea Mifsud; Lieuwe B. Leene; Jiawei Shen; Christos Papavassiliou; Timothy G.  Constandinou; Themis Prodromakis

Hybrid CMOS/Memristor Circuit Design Methodology

Sachin Maheshwari, Spyros Stathopoulos, Jiaqi Wang, Alex Serb, Yihan Pan, Andrea Mifsud, Lieuwe B. Leene, Jiawei Shen, Christos Papavassiliou, Timothy G. Constandinou, Themis Prodromakis

School of Engineering

Research output: Working paper › Preprint

Abstract

RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

Original language	Undefined/Unknown
Publisher	ArXiv
Publication status	Published - 3 Dec 2020

Access to Document

https://arxiv.org/abs/2012.02267Licence: Creative Commons: Attribution (CC-BY)

Cite this

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title = "Hybrid CMOS/Memristor Circuit Design Methodology",

abstract = "RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.",

author = "Sachin Maheshwari and Spyros Stathopoulos and Jiaqi Wang and Alex Serb and Yihan Pan and Andrea Mifsud and Leene, {Lieuwe B.} and Jiawei Shen and Christos Papavassiliou and Constandinou, {Timothy G.} and Themis Prodromakis",

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T1 - Hybrid CMOS/Memristor Circuit Design Methodology

AU - Maheshwari, Sachin

AU - Stathopoulos, Spyros

AU - Wang, Jiaqi

AU - Serb, Alex

AU - Pan, Yihan

AU - Mifsud, Andrea

AU - Leene, Lieuwe B.

AU - Shen, Jiawei

AU - Papavassiliou, Christos

AU - Constandinou, Timothy G.

AU - Prodromakis, Themis

PY - 2020/12/3

Y1 - 2020/12/3

N2 - RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

AB - RRAM technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate with examples an end-to-end design flow for RRAM-based electronics, from the introduction of a custom RRAM model into our chosen CAD tool to performing layout-versus-schematic and post-layout checks including the RRAM device. We envisage that this step-by-step guide to introducing RRAM into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with RRAM-enhanced systems.

M3 - Preprint

BT - Hybrid CMOS/Memristor Circuit Design Methodology

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