Impact of line edge roughness on ReRAM uniformity and scaling

Vassilios Constantoudis*, George Papavieros, Panagiotis Karakolis, Ali Khiat, Themistoklis Prodromakis, Panagiotis Dimitrakis

*Corresponding author for this work

Research output: Contribution to journalArticlepeer-review

Abstract / Description of output

We investigate the effects of Line Edge Roughness (LER) of electrode lines on the uniformity of Resistive Random Access Memory (ReRAM) device areas in cross-point architectures. To this end, a modeling approach is implemented based on the generation of 2D cross-point patterns with predefined and controlled LER and pattern parameters. The aim is to evaluate the significance of LER in the variability of device areas and their performances and to pinpoint the most critical parameters and conditions. It is found that conventional LER parameters may induce >10% area variability depending on pattern dimensions and cross edge/line correlations. Increased edge correlations in lines such as those that appeared in Double Patterning and Directed Self-assembly Lithography techniques lead to reduced area variability. Finally, a theoretical formula is derived to explain the numerical dependencies of the modeling method.

Original languageEnglish
Article number3972
Issue number23
Publication statusPublished - 30 Nov 2019

Keywords / Materials (for Non-textual outputs)

  • Line edge roughness (LER)
  • Lithography
  • Modeling
  • Resistive random access memory (ReRAM)
  • Uniformity
  • Variability


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