Implementation of Highly Pipelined Datapaths on a Reconfigurable Asynchronous Substrate

Khodor Fawaz, Tughrul Arslan, Iain Lindsay

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In programmable logic devices, the timing requirements change depending on what datapath is being mapped and the level of pipelining required. The added flexibility of such architectures translates to complexity in the design of their clocking scheme, both on the silicon and software level. Using asynchronous techniques to design the programmable elements and interconnects simplifies this problem by replacing the global clock signal with local handshaking. In asynchronous programmable devices, the handshaking protocol implements communication and synchronisation among the components of any mapped datapath irrespective of its length.

This paper describes the design of an asynchronous substrate for implementing highly pipelined datapaths. A novel technique for conditional acknowledge synchronisation was used in the interconnect design. Two asynchronous arrays of coarse-grain adders and multipliers were built and compared with an equivalent clocked architecture. For a sample FFT, our asynchronous designs showed a reduction of up to 10% in energy consumption and 4.5% in area, which came at a cost of a 2.5% reduction in throughput over the equivalent synchronous implementation.

Original languageEnglish
Title of host publicationPROCEEDINGS OF THE 2009 NASA/ESA CONFERENCE ON ADAPTIVE HARDWARE AND SYSTEMS
Place of PublicationLOS ALAMITOS
PublisherInstitute of Electrical and Electronics Engineers
Pages112-119
Number of pages8
ISBN (Print)978-0-7695-3714-6
DOIs
Publication statusPublished - 2009
Event4th NASA/ESA Conference on Adaptive Hardware and Systems - San Francisco
Duration: 29 Jul 20091 Aug 2009

Conference

Conference4th NASA/ESA Conference on Adaptive Hardware and Systems
CitySan Francisco
Period29/07/091/08/09

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