Increasing Cache Capacity via Critical-words-Only Cache

Cheng-Chieh Huang, Vijay Nagarajan

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Current processors have multiple levels of caches. Choosing the right cache size for each level is critical for performance. The first-level cache (L1) is typically small, in order to match the speed of the processor. The lower level caches, on the other hand, are typically large, in order to reduce capacity misses. However, situations may arise in which the size of a lower level cache cannot be increased beyond a point - for example, recent Intel multi-core processors (including Nehalem and Sandy Bridge) have only 256 kB private L2 caches per core - which adversely affects the performance of benchmarks which have large working set sizes. In this paper, we propose a novel cache design known as the critical-words-only cache (co-cache) for increasing the effective cache capacity. Our approach involves rethinking the notion of cache blocks; instead of storing all the words that belong to a cache block, we only store the critical words, where the critical words are the words that are generally accessed before the others. Our experiments show that with our design a 256 kB L2 performs as well as a 512 kB conventional L2 cache on average.
Original languageEnglish
Title of host publicationComputer Design (ICCD), 2014 32nd IEEE International Conference on
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages8
Publication statusPublished - 19 Oct 2014
Event32nd IEEE International Conference on Computer Design - Seoul, Korea, Democratic People's Republic of
Duration: 19 Oct 201422 Oct 2014


Conference32nd IEEE International Conference on Computer Design
CountryKorea, Democratic People's Republic of

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