Instruction Buffers

R. N. Ibbett, N. P. Topham

Research output: Chapter in Book/Report/Conference proceedingChapter


In dealing with operand accessing in earlier chapters we considered various techniques used to overcome the disparity between processing speed and main store accessing rate. This problem also impinges on instruction accessing, since for efficient operation instructions must also be supplied to the processor at a rate matching its execution rate. In the case of instruction accessing, however, the problem is ameliorated by the fact that most instructions are obeyed sequentially and the main store word size is normally such that one word fetched from main store can contain several instructions. Furthermore, with an interleaved store, successive accesses for sequential instructions reference each stack in turn and are not held up by cycle time effects. Thus store requests can be made in advance of the corresponding instruction being required and the replies buffered until they are needed for execution. This pre-fetching technique is used in almost all high performance pipelined processors. A significant proportion of instructions cause control transfers, however, and each such transfer requires a request to be made to the store for a new sequence of instructions. Thus although the accessing rate for instructions can normally be matched satisfactorily to the processing rate, the access time for the first instruction of a new sequence can result in a long delay to the processor.
Original languageEnglish
Title of host publicationArchitecture of High Performance Computers
Subtitle of host publicationVolume I: Uniprocessors and vector processors
Place of PublicationLondon
PublisherMacmillan Education UK
Number of pages22
ISBN (Electronic)978-1-349-19757-6
ISBN (Print)978-0-333-46362-8
Publication statusPublished - 1989

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