Instruction packing: reducing power and delay of the dynamic scheduling logic

Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The instruction scheduling logic used in modern superscalar microprocessors often relies on associative searching of the issue queue entries to dynamically wakeup instructions for the execution. Traditional designs use one issue queue entry for each instruction, regardless of the actual number of operands actively used in the wakeup process. In this paper we propose Instruction Packing - a novel microarchitectural technique that reduces both the delay and the power consumption of the issue queue by sharing the associative part of an issue queue entry between two instructions, each with at most one non-ready register source operand at the time of dispatch. Our results show that Instruction Packing provides a 39% reduction of the whole issue queue power and 21.6% reduction in the wakeup delay with as little as 0.4% IPC degradation on the average across the simulated SPEC benchmarks
Original languageEnglish
Title of host publicationProceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005
PublisherACM
Pages30-35
Number of pages6
ISBN (Print)1-59593-137-6
DOIs
Publication statusPublished - 2005

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