Interconnection Networks

R. N. Ibbett, N. P. Topham

Research output: Chapter in Book/Report/Conference proceedingChapter

Abstract / Description of output

The first half of this book is concerned essentially with the ways in which massive data parallelism can be processed by large numbers of processing elements, acting in concert, under the control of a single sequence of common instructions. As outlined in chapter 2, these processing elements may either share a common memory or be provided with their own private memories. This leads to the two general array architectures shown in figure 2.3 and figure 2.4. In both cases an interconnection structure is required, either to provide all processors with equal access to a number of parallel memory modules, or to provide a data communication mechanism between processing elements. The second half of this book is concerned with parallelism of a different form; where large numbers of processors cooperate asynchronously on different parts of the same task, either through shared access to the data structures which define the problem or through a distribution of the problem coupled with the occasional exchange of messages between processors. Again, in both of these cases some form of interconnection structure is required; either to provide concurrent access to a shared memory structure, or to provide a message-routing facility.
Original languageEnglish
Title of host publicationArchitecture of High Performance Computers Volume II
Subtitle of host publicationArray processors and multiprocessor systems
Place of PublicationNew York, NY
PublisherSpringer New York
Number of pages21
ISBN (Electronic)978-1-4899-6701-5
ISBN (Print)978-1-4899-6703-9
Publication statusPublished - 1989


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