Investigation of output filter topologies for a Parallel Hybrid Converter based on Si-IGBTs and partially-rated SiC-MOSFETs

This paper presents an investigation of different output filter topologies for the parallel hybrid converter (PHC), an AC-DC converter which employs dual SiC-MOSFET and Si-IGBT bridges. Building on previous work a Finite Control Set Model Predictive Control (FCS-MPC) algorithm which simultaneously control the switching of both converters to achieve gains in efficiency and power quality with minimal use of expensive SiC devices. This paper analyses the effect of the filter topology, MPC cost function constraints and output filter inductance ratio on the common mode current, average Si switching frequency and electrical power quality measured by total current harmonic distortion (THD) in point of common coupling (PCC). This paper achieves the reduction of Si switching frequency bounded to a THD of 2 %. Finally, an inter-converter common mode voltage constraint is implemented to address the zero sequence circulating current.