Leakage Immune Modified Cross Coupled Inverter Based MI-12T SRAM in Sub-Threshold Regime

Priya Gupta, Pawan Sharma, Srinjoy Mitra

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract / Description of output

Stable SRAM cells at ultra-low power supply voltage is an important design requirement for digital circuits in deep sub-micron region. The paper presents in-depth analysis of low-power, variability-aware, stable 12T SRAM cell using 45nm standard CMOS technology. The high leakage current is reduced by using ON/OFF logic pair. The Modified Inverter-12T (MI-12T) cell obtains 2.5x higher write-SNM and 1.6x improved read-SNM than Standard 6T (S6T) SRAM cell. Varying V DD 0.2 V to 0.4 V, the MI-12T SRAM cell achieves lower average read delay (read access time), 3.57x less average write delay (write access time), 1.476x lower average hold power consumption in comparison to S6T. Thus, the simulation results reveal that MI-12T has high cell stability and enhanced data maintenance ability at 0.4V.
Original languageEnglish
Title of host publication2019 International Conference on Computing, Electronics & Communications Engineering (iCCECE)
PublisherInstitute of Electrical and Electronics Engineers
DOIs
Publication statusPublished - 27 Dec 2019

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