TY - GEN
T1 - Limitations and precision requirements for read-out of passive, linear, selectorless RRAM arrays
AU - Serb, Alexander
AU - Redman-White, William
AU - Papavassiliou, C.
AU - Berdan, Radu
AU - Prodromakis, Themistoklis
PY - 2015/7/30
Y1 - 2015/7/30
N2 - A practical system for reading out from linear, multi-level, selectorless Resistive Random Access Memory (RRAM) arrays based on a Trans-Impedance Amplifier (TIA) approach is presented and studied. SPICE simulation of the core of the system is performed in order to extract predicted sensitivity to error factors such as non-zero TIA offsets and access resistance. A physical implementation of the system is then tested on a small, 12 × 12 reference array and measured results show its ability to decode absolute resistive states in the range of 1 kμ-220 kω within ≈ 11% tolerance.
AB - A practical system for reading out from linear, multi-level, selectorless Resistive Random Access Memory (RRAM) arrays based on a Trans-Impedance Amplifier (TIA) approach is presented and studied. SPICE simulation of the core of the system is performed in order to extract predicted sensitivity to error factors such as non-zero TIA offsets and access resistance. A physical implementation of the system is then tested on a small, 12 × 12 reference array and measured results show its ability to decode absolute resistive states in the range of 1 kμ-220 kω within ≈ 11% tolerance.
UR - http://www.scopus.com/inward/record.url?scp=84946239756&partnerID=8YFLogxK
U2 - 10.1109/ISCAS.2015.7168602
DO - 10.1109/ISCAS.2015.7168602
M3 - Conference contribution
AN - SCOPUS:84946239756
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 189
EP - 192
BT - 2015 IEEE International Symposium on Circuits and Systems, ISCAS 2015
PB - Institute of Electrical and Electronics Engineers
T2 - IEEE International Symposium on Circuits and Systems, ISCAS 2015
Y2 - 24 May 2015 through 27 May 2015
ER -